With the rapid growth of wireless and portable consumer electronic devices, there have been increasing demands for new technological advancements with more and more functionalities being crammed into battery-operated devices. This phenomenon has resulted in increasing design and verification challenges for low-power applications.
The challenges include minimizing leakage power dissipation, designing efficient packaging and cooling systems for high-power integrated circuits, verifying functionalities of low-power or no power situations early in the design. Such power management issues become even more critical in view of the continuous shrinking of device dimensions with the next generation of semiconductor processing technology. Addressing such power management issues is critical in the integrated circuit design flow for portable consumer electronic devices.
Existing power optimization and implementation techniques are typically applied at the physical implementation phase of the design process. Certain power management techniques can only be implemented at the physical level after circuit synthesis. These power techniques can only be implemented at the physical level after circuit synthesis. These power management design techniques may significantly change the design intent, yet none of the intended behavior can be captured in the RTL of the design. This deficiency creates a gap in the RTL to Graphic Data System II (GDSII) implementation and verification flow where the original RTL can no longer be relied upon as a correct representation of the design, and thus cannot be used to verify the final netlist implementation containing power management implementations.
Therefore, there is a need for incorporating power information of the circuit to address the deficiencies of the existing design methodologies early on in the design process. Specifically, there is a need for incorporating power information in the early design cycles and applying the power information to the entire design flow of verification, validation, synthesis, test, physical synthesis, routing, analysis and signoff tool. In particular, there is a need to ensure proper state retention and state loss behavior of a power domain in an RTL design environment.